This invention relates to the electronic computers having a dynamic operative memory and an information refreshing arrangement.
The use of dynamic memories according to the MOS technology has been progressively extended in the field of the electronic computers, due to the low cost thereof with respect to the static memories. These memories are recorded by charging a capacitive element, forming the memory location, and must be recharged or refreshed at a rather high frequency, comparable with the length of the operative cycles of the computer. Therefore, the addresses of the memory, necessary for the computing operations, must be clearly distinguished from those necessary for the information refreshing operations.
In a known information refreshing arrengement, when the refreshing operation are effected, the addressing of the memory for reading or writing operations are prevented. This arrangement thus, on one hand results in a lower speed operation, on the other hand requires additional timing means and/or frequency dividers for generating the timing of the refreshing cycle, and additional circuitry for selectively starting the refreshing cycle and the operation cycle without overlapping.